//2024-3-1 姜青羊
//日常练习

`timescale 1ns/10ps
module comp_conv (
                        a,
                        a_comp
                    );

input[7:0]              a;
output[7:0]             a_comp;

wire[7:0]               b;

assign                  b={a[7],a[6:0]+1};

assign                  a_comp=a[7]?b:a;
    
endmodule


//------testbench-------

module tb_comp_conv ();

reg[7:0]                aa;
wire[7:0]               ac;

comp_conv u_comp_conv (
                        .a(aa),
                        .a_comp(ac)
                    );

initial begin
                         aa<=8'b0000_0000;
            #3000        $stop;
end

always      #10          aa=aa+1;         

endmodule