//2024-2-1 姜青羊
//7段显示译码器抄写

`timescale 1ns/10ps
module seg_dec (
                        num,
                        a_g
               );

input[3:0]              num;
output[7:0]             a_g;// a_g[6:0]-->{a,b,c,d,e,f,g}

reg[7:0]                a_g;

always @(*) begin
    
    case(num)
    4'd0: a_g=7'b1111_110;
    4'd1: a_g=7'b0110_000;
    4'd2: a_g=7'b1101_101;
    4'd3: a_g=7'b1111_001;
    4'd4: a_g=7'b0110_011;
    4'd5: a_g=7'b1011_011;
    4'd6: a_g=7'b1011_111;
    4'd7: a_g=7'b1110_000;
    4'd8: a_g=7'b1111_111;
    4'd9: a_g=7'b1111_011;
    default: a_g=7'b0000_001;
    
    endcase

end

endmodule


//----testbench-----

module tb_seg_dec ();

reg[3:0]                 n;
wire[7:0]                a;

initial begin
                         n=4'd0;
            #200         $stop;          
end

always  #10              n=n+1;

endmodule