//2023-11-11 
//ѡһ߼ʺð䣩

`timescale 1ns/10ps
module fn_sw (
                    a,
                    b,
                    sel,
                    y
             );

input               a,b,sel;
output              y;

assign              y=sel?(a^b):(a&b);
    
endmodule

//-----testbench------

module tb_fn_sw ();

reg                 aa,bb,ss;
wire                yy;

initial begin
                    ss=0; aa=0; bb=0;
         #10        ss=0; aa=0; bb=1;
         #10        ss=0; aa=1; bb=0;
         #10        ss=0; aa=1; bb=1;
         #10        ss=1; aa=0; bb=0;
         #10        ss=1; aa=0; bb=1;
         #10        ss=1; aa=1; bb=0;
         #10        ss=1; aa=1; bb=1;
                    $stop;
end


fn_sw u_fn_sw (
                    .a(aa),
                    .b(bb),
                    .sel(ss),
                    .y(yy)
             );

endmodule