//2023-8-21, Jiang Qingyang(姜青羊)
//either-or logic design(二选一逻辑设计，always语句块实现)

`timescale 1ns/10ps
module fn_sw (
                a,
                b,
                sel,
                y
                );

input           a;
input           b;
input           sel;
output          y;

//assign          y=sel?(a^b):(a&b);  
//用always语句块实现组合逻辑；

reg             y;

always @(a or b or sel) begin
   
   if(sel==1)begin  
      y<=a^b;
   end
   else begin
      y<=a&b; 
   end

end

endmodule

//------testbench of fn_sw--------

module tb_fn_sw ();

reg              a,b,sel;
wire             y;

initial begin
                a<=0;b<=0;sel<=0;   //按二级制加法来遍历
                       #10;         //把#10放放在一句前面也行
                a<=0;b<=0;sel<=1;
                       #10;
                a<=0;b<=1;sel<=0;
                       #10;
                a<=0;b<=1;sel<=1;
                       #10;
                a<=1;b<=0;sel<=0;
                       #10;
                a<=1;b<=0;sel<=1;
                       #10;
                a<=1;b<=1;sel<=0;
                       #10;
                a<=1;b<=1;sel<=1;
                       #10;
                $stop;     


end



fn_sw u_fn_sw (
                .a(a),
                .b(b),
                .sel(sel),
                .y(y)
                );
    
endmodule