//2023-9-24 (姜青羊)
//cells(各种常用基本组合逻辑单元)

module moduleName (
                    a      ,
                    b      ,
                    c      ,
                    d      ,
                    sel    ,
                    y_buf  ,//缓冲器buffer
                    y_not  ,
                    y_or   ,
                    y_xor  ,  //异或
                    y_nand ,  //与非 
                    y_nor  ,  //或非
                    y_nxor , //同或（异或非）
                    y_mux  ,
                    y_add  //加法
                  );

input   wire         a, b, c, d, sel;
output  wire         y_buf, y_not, y_and;
output  wire         y_or, y_xor;
output  wire         y_nand, y_nor, y_nxor;
output  wire         y_mux;
output  wire[1:0]    y_add;  //[1:0]是两比特，写成[2:1]也行，只是很怪
                             //与c不同，在verilog里可以随意指定位宽
assign  y_buf  = a;
assign  y_not  = ~a;
assign  y_and  = a & b;
assign  y_or   = a | b;
assign  y_xor  = a ^ b;
assign  y_nand = ~(a & b);
assign  y_nor  = ~(a | b);
assign  y_nxor = ~(a ^ b);
assign  y_mux  = (sel)?b:a;
assign  y_add  = {1'b0,a}+{1'b0,b};  //{}是bite拼接的意思，先拼成两bite
                                     //再用两bite加
    
endmodule