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HardwareProfile.h 4.02 KB
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Hell-Prototypes 提交于 2013-11-01 10:23 . add fpga app switch code
//*********************************************************************
// Copyright (C) 2013 Hell Prototypes / www.hellprototypes.com
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//********************************************************************
#ifndef HARDWAREPROFILE_H
#define HARDWAREPROFILE_H
//Uncomment one of the following lines to make the output HEX of this
// project work with the HID or Microchip Bootloader
//#define PROGRAMMABLE_WITH_USB_HID_BOOTLOADER
#define PROGRAMMABLE_WITH_USB_MCHPUSB_BOOTLOADER
#define CLOCK_FREQ 48000000 // Clock frequency in Hz.
#define MIPS 12 // Number of processor instructions per microsecond.
#define INPUT_PIN 1
#define OUTPUT_PIN 0
/** Pin definition macros *******************************************/
#define TRIS( P, B ) ( TRIS ## P ## bits.TRIS ## P ## B )
#define PORT( P, B ) ( PORT ## P ## bits.R ## P ## B )
#define PORT_ASM( P, B ) PORT ## P ##, B, ACCESS
#define LATCH( P, B ) ( LAT ## P ## bits.LAT ## P ## B )
#define LATCH_ASM( P, B ) LAT ## P ##, B, ACCESS
/** FPGA DONE pin***************************************************/
#define DONE_PORT C
#define DONE_BIT 6
#define DONE_MASK ( 1 << DONE_BIT )
#define DONE_TRIS TRIS( C, 6 )
#define DONE PORT( C, 6 )
#define DONE_ASM PORT_ASM( C, 6 )
#define INIT_DONE() DONE_TRIS = INPUT_PIN
/** FPGA PROG# pin control ******************************************/
#define PROGB_PORT C
#define PROGB_BIT 5
#define PROGB_MASK ( 1 << PROGB_BIT )
#define PROGB_TRIS TRIS( C, 5 )
#define PROGB LATCH( C, 5 )
#define PROGB_ASM PORT_ASM( C, 5 )
#define INIT_PROGB() PROGB = 0, PROGB_TRIS = OUTPUT_PIN
/** FPGA clock pin control ******************************************/
#define FPGACLK_PORT C
#define FPGACLK_BIT 4
#define FPGACLK_MASK ( 1 << FPGACLK_BIT )
#define FPGACLK_TRIS TRIS( C, 4 )
#define FPGACLK LATCH( C, 4 )
#define FPGACLK_ON() PSTRCON = 0b00000010
#define FPGACLK_OFF() PSTRCON = 0
// Setup the FPGA clock by initializing the PWM B channel to output a 12 MHz clock.
#define INIT_FPGACLK() FPGACLK_OFF(), FPGACLK = 0, FPGACLK_TRIS = OUTPUT_PIN, \
T2CON = 0b00000100, PR2 = 0, CCPR1L = 0, CCP1CON = 0b00101100
/** LED *************************************************************/
#define LED_PORT C
#define LED_BIT 3
#define LED_MASK ( 1 << LED_BIT )
#define LED_TRIS TRIS( C, 3 )
#define LED LATCH( C, 3 )
#define LED_ASM PORT_ASM( C, 3 )
#define LED_OFF() LED = 0
#define LED_ON() LED = 1
#define LED_TOGGLE() LED = !LED
#define INIT_LED() LED_OFF(), LED_TRIS = OUTPUT_PIN
/** KEY ************************************************************/
#define KEY_PORT A
#define KEY_BIT 3
#define KEY_MASK ( 1 << KEY_BIT )
#define KEY_TRIS TRIS( A, 3 )
#define KEY PORT( A, 3 )
#define KEY_ASM PORT_ASM( A, 3 )
#define INIT_KEY() ANSELH = 0, INTCON2bits.NOT_RABPU = 0
/** Some common uC bits ********************************************/
// ALU carry bit.
#define CARRY_POS 0
#define CARRY_BIT_ASM STATUS, CARRY_POS, ACCESS
// MSSP buffer-full bit.
#define MSSP_BF_POS 0
#define MSSP_BF_ASM WREG, MSSP_BF_POS, ACCESS
// Converse of using ACCESS flag for destination register.
#define TO_WREG 0
#endif
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