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Change_History 4.42 KB
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2023/03/12 V1.16 Wilson Chen add floating port support as a new issue
2023/03/10 V1.15 Wilson Chen change source file to be ".vp"
change temp file to $mod_name.vpp
add `ifdef support on port connection from a new issue
2023/02/10 V1.13 Wilson Chen fix bug of `define handler & print
2023/02/08 V1.12 Wilson Chen fix Instance Connect 'bxx 'hxx bug
add missed test_DAC.v
2023/02/07 V1.11 Wilson Chen fix Verilog ports parser, support & test more strange style
fix instance ports printing bugs for specail cases
2023/02/05 V1.10 Wilson Chen Decide to use JSON file as Hierarchy Integration solution, but NOT IPXACT!
Add TransIPX to translate IPXACT to JSON for easy understanding
Add GenModJson to export Modules' name & interfaces & ports to JSON file
Update Instance function to instance from JSON file with interfaces & ports
Change HDLGenIpxIntf.pm to real package
2023/01/26 V1.05 Wilson Chen Add functions to export Interfaces & Ports for Hierarchy Integration
need to update: export Interfaces & Ports to IPXACT file
2023/01/08 V1.02 Wilson Chen fix an auto signal width-learning bug
add missed AsyncIntfGen.pm
update license date
2022/12/25 V1.01 Wilson Chen Add AddParam function from an open request
2022/12/12 V1.00 Wilson Chen fix some typo & format
Beta release
2022/11/30 V0.99 Wilson Chen support inhouse function module generation:
use JSON file for paramaters
use ePerl Template file for custom design
2022/11/26 V0.94 Wilson Chen fix AutoWarning function
support PARAMETER & DEFINE on auto signal declare
sig declare will change to final value but not PARAM/DEFINE name
2022/11/18 V0.93 Wilson Chen fix LHS multi-signal: handle {wire0,wire1...} = {sig0[...], sig1[...] ...}
2022/11/14 V0.92 Wilson Chen update AutoInstSigs to do width-learning from all Instance & Assignments
need to update: handle assign LHS multi-signal (FIXME)
2022/11/12 V0.91 Wilson Chen add AutoWarning feature, but not perfect yet (FIXME)
2022/11/10 V0.90 Wilson Chen add Instance inputs & outputs no connection warnings
2022/11/08 V0.86 Wilson Chen use Verilog::Netlist to handle Assignments
change "AutoInstWire" to "AutoInstSig" as "reg" is possible for Instance's port connection
"reg" is not perfect but should work in most case
2022/10/14 V0.85 Wilson Chen add ShowIntf & ShowIPX function
2022/10/11 V0.84 Wilson Chen fix Instance bug(return)
update colorful information print
2022/10/10 V0.83 Wilson Chen update Instance to support IPXACT
update Instance for multi-parameter support
fix Instance function bug($C_done)£»
2022/10/08 V0.82 Wilson Chen change ExptIPX function name (remove IPX)
add RmIntfPort function & usage
add CallCmd function & usage
add 3 DTI(Data Transfer Interface) function & usage
fix Connect bug($n)
2022/9/30 V0.81 Wilson Chen fix a few bugs
change from temp file to mem array for internal database
2022/6/01 V0.8 Wilson Chen bugs & typo cleaning
Alpha release
2022/5/20 V0.7 Wilson Chen support SV/RTL/HASH interface customize
2022/4/30 V0.6 Wilson Chen support IPXACT & XML interface & port
2022/4/22 V0.5 Wilson Chen support Interface Connect
2022/4/18 V0.4 Wilson Chen support AMBA Interface
2022/4/16 V0.3 Wilson Chen initial function done(SRC & Instance & Connect)
2022/4/10 V0.2 Wilson Chen enable embedded Perl & Python
2022/4/05 V0.1 Wilson Chen project initial
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