# 0 "official_device/cv1800b_milkv_duo_sd.dts"
# 0 "<built-in>"
# 0 "<command-line>"
# 1 "official_device/cv1800b_milkv_duo_sd.dts"
/dts-v1/;
# 1 "official_device/cv180x_base_riscv.dtsi" 1
# 1 "official_device/irq.h" 1
# 2 "official_device/cv180x_base_riscv.dtsi" 2
# 1 "official_device/gpio.h" 1
# 3 "official_device/cv180x_base_riscv.dtsi" 2
# 1 "official_device/cv180x-resets.h" 1
# 4 "official_device/cv180x_base_riscv.dtsi" 2
# 1 "official_device/cv180x-clock.h" 1
# 5 "official_device/cv180x_base_riscv.dtsi" 2
# 1 "official_device/thermal.h" 1
# 6 "official_device/cv180x_base_riscv.dtsi" 2
# 1 "official_device/cv180x-dmamap.h" 1
# 7 "official_device/cv180x_base_riscv.dtsi" 2
# 19 "official_device/cv180x_base_riscv.dtsi"
/memreserve/ 0x80000000 0x80000;


# 1 "official_device/cv180x_base.dtsi" 1

/ {
 compatible = "cvitek,cv180x";

 #size-cells = <0x2>;
 #address-cells = <0x2>;

 top_misc:top_misc_ctrl@3000000 {
  compatible = "syscon";
  reg = <0x0 0x03000000 0x0 0x8000>;
 };

 clk_rst: clk-reset-controller {
  #reset-cells = <1>;
  compatible = "cvitek,clk-reset";
  reg = <0x0 0x03002000 0x0 0x8>;
 };

 osc: oscillator {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <25000000>;
  clock-output-names = "osc";
 };

 clk: clock-controller {
  compatible = "cvitek,cv180x-clk";
  reg = <0x0 0x03002000 0x0 0x1000>;
  clocks = <&osc>;
  #clock-cells = <1>;
 };

 rst: reset-controller {
  #reset-cells = <1>;
  compatible = "cvitek,reset";
  reg = <0x0 0x03003000 0x0 0x10>;
 };

 restart: restart-controller {
  compatible = "cvitek,restart";
  reg = <0x0 0x05025000 0x0 0x2000>;
 };

 tpu {
  compatible = "cvitek,tpu";
  reg-names = "tdma", "tiu";
  reg = <0x0 0x0C100000 0x0 0x1000>,
     <0x0 0x0C101000 0x0 0x1000>;
  clocks = <&clk 12>, <&clk 13>;
  clock-names = "clk_tpu_axi", "clk_tpu_fab";
  resets = <&rst 7>, <&rst 8>, <&rst 9>;
  reset-names = "res_tdma", "res_tpu", "res_tpusys";
 };

 mon {
  compatible = "cvitek,mon";
  reg-names = "pcmon", "ddr_ctrl", "ddr_phyd", "ddr_aximon", "ddr_top";
  reg = <0x0 0x01040000 0x0 0x1000>,
     <0x0 0x08004000 0x0 0x1000>,
     <0x0 0x08006000 0x0 0x1000>,
     <0x0 0x08008000 0x0 0x1000>,
     <0x0 0x0800A000 0x0 0x1000>;
 };

 wiegand0 {
  compatible = "cvitek,wiegand";
  reg-names = "wiegand";
  reg = <0x0 0x03030000 0x0 0x1000>;
  clocks = <&clk 126>, <&clk 127>;
  clock-names = "clk_wgn", "clk_wgn1";
  resets = <&rst 86>;
  reset-names = "res_wgn";
 };

 wiegand1 {
  compatible = "cvitek,wiegand";
  reg-names = "wiegand";
  reg = <0x0 0x03031000 0x0 0x1000>;
  clocks = <&clk 126>, <&clk 128>;
  clock-names = "clk_wgn", "clk_wgn1";
  resets = <&rst 87>;
  reset-names = "res_wgn";
 };

 wiegand2 {
  compatible = "cvitek,wiegand";
  reg-names = "wiegand";
  reg = <0x0 0x03032000 0x0 0x1000>;
  clocks = <&clk 126>, <&clk 129>;
  clock-names = "clk_wgn", "clk_wgn1";
  resets = <&rst 88>;
  reset-names = "res_wgn";
 };

 saradc {
  compatible = "cvitek,saradc";
  reg-names = "top_domain_saradc", "rtc_domain_saradc";
  reg = <0x0 0x030F0000 0x0 0x1000>, <0x0 0x0502c000 0x0 0x1000>;
  clocks = <&clk 18>;
  clock-names = "clk_saradc";
  resets = <&rst 52>;
  reset-names = "res_saradc";
 };

 rtc {
  compatible = "cvitek,rtc";
  reg = <0x0 0x05026000 0x0 0x1000>,<0x0 0x05025000 0x0 0x1000>;
  clocks = <&clk 16>;
  clock-names = "clk_rtc";
 };

 cvitek-ion {
  compatible = "cvitek,cvitek-ion";

  heap_carveout@0 {
   compatible = "cvitek,carveout";
   memory-region = <&ion_reserved>;
  };
 };

 sysdma_remap {
  compatible = "cvitek,sysdma_remap";
  reg = <0x0 0x03000154 0x0 0x10>;
  ch-remap = <0 5 2 3
     38 38 4 7>;
  int_mux_base = <0x03000298>;
 };

 dmac: dma@0x4330000 {
  compatible = "snps,dmac-bm";
  reg = <0x0 0x04330000 0x0 0x1000>;
  clock-names = "clk_sdma_axi";
  clocks = <&clk 41>;

  dma-channels = /bits/ 8 <8>;
  #dma-cells = <3>;
  dma-requests = /bits/ 8 <16>;
  chan_allocation_order = /bits/ 8 <0>;
  chan_priority = /bits/ 8 <1>;
  block_size = <1024>;
  dma-masters = /bits/ 8 <2>;
  data-width = <4 4>;
  axi_tr_width = <4>;
  block-ts = <15>;
 };

 watchdog0: cv-wd@0x3010000 {
  compatible = "snps,dw-wdt";
  reg = <0x0 0x03010000 0x0 0x1000>;
  resets = <&rst 48>;
  clocks = <&pclk>;
 };

 pwm0: pwm@3060000 {
  compatible = "cvitek,cvi-pwm";
  reg = <0x0 0x3060000 0x0 0x1000>;
  clocks = <&clk 48>;
  #pwm-cells = <1>;
 };

 pwm1: pwm@3061000 {
  compatible = "cvitek,cvi-pwm";
  reg = <0x0 0x3061000 0x0 0x1000>;
  clocks = <&clk 48>;
  #pwm-cells = <2>;
 };

 pwm2: pwm@3062000 {
  compatible = "cvitek,cvi-pwm";
  reg = <0x0 0x3062000 0x0 0x1000>;
  clocks = <&clk 48>;
  #pwm-cells = <3>;
 };

 pwm3: pwm@3063000 {
  compatible = "cvitek,cvi-pwm";
  reg = <0x0 0x3063000 0x0 0x1000>;
  clocks = <&clk 48>;
  #pwm-cells = <4>;
 };

 pclk: pclk {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <25000000>;
 };

 spinand:cv-spinf@4060000 {
  compatible = "cvitek,cv1835-spinf";
  reg = <0x0 0x4060000 0x0 0x1000>;
  reg-names = "core_mem";
  bus-width = <4>;
  dmas = <&dmac 4 1 1
   &dmac 5 1 1>;
  dma-names = "rx","tx";
 };

 spif:cvi-spif@10000000 {
  compatible = "cvitek,cvi-spif";
  bus-num = <0>;
  reg = <0x0 0x10000000 0x0 0x10000000>;
  reg-names = "spif";
  sck-div = <3>;
  sck_mhz = <300>;
  spi-max-frequency = <75000000>;
  spiflash {
   compatible = "jedec,spi-nor";
   spi-rx-bus-width = <4>;
   spi-tx-bus-width = <4>;
  };
 };

 spi0:spi0@04180000 {
  compatible = "snps,dw-apb-ssi";
  reg = <0x0 0x04180000 0x0 0x10000>;
  clocks = <&clk 110>;
  #address-cells = <1>;
  #size-cells = <0>;
 };

 spi1:spi1@04190000 {
  compatible = "snps,dw-apb-ssi";
  reg = <0x0 0x04190000 0x0 0x10000>;
  clocks = <&clk 110>;
  #address-cells = <1>;
  #size-cells = <0>;
 };

 spi2:spi2@041A0000 {
  compatible = "snps,dw-apb-ssi";
  reg = <0x0 0x041A0000 0x0 0x10000>;
  clocks = <&clk 110>;
  #address-cells = <1>;
  #size-cells = <0>;
 };

 spi3:spi3@041B0000 {
  compatible = "snps,dw-apb-ssi";
  reg = <0x0 0x041B0000 0x0 0x10000>;
  clocks = <&clk 110>;
  #address-cells = <1>;
  #size-cells = <0>;






 };

 uart0: serial@04140000 {
  compatible = "snps,dw-apb-uart";
  reg = <0x0 0x04140000 0x0 0x1000>;
  clock-frequency = <25000000>;
  reg-shift = <2>;
  reg-io-width = <4>;
  status = "okay";
 };

 uart1: serial@04150000 {
  compatible = "snps,dw-apb-uart";
  reg = <0x0 0x04150000 0x0 0x1000>;
  clock-frequency = <25000000>;
  reg-shift = <2>;
  reg-io-width = <4>;
  status = "disabled";
 };

 uart2: serial@04160000 {
  compatible = "snps,dw-apb-uart";
  reg = <0x0 0x04160000 0x0 0x1000>;
  clock-frequency = <25000000>;
  reg-shift = <2>;
  reg-io-width = <4>;
  status = "disabled";
 };

 uart3: serial@04170000 {
  compatible = "snps,dw-apb-uart";
  reg = <0x0 0x04170000 0x0 0x1000>;
  clock-frequency = <25000000>;
  reg-shift = <2>;
  reg-io-width = <4>;
  status = "disabled";
 };

 uart4: serial@041C0000 {
  compatible = "snps,dw-apb-uart";
  reg = <0x0 0x041C0000 0x0 0x1000>;
  clock-frequency = <25000000>;
  reg-shift = <2>;
  reg-io-width = <4>;
  status = "disabled";
 };

 gpio0: gpio@03020000 {
  compatible = "snps,dw-apb-gpio";
  reg = <0x0 0x03020000 0x0 0x1000>;
  #address-cells = <1>;
  #size-cells = <0>;

  porta: gpio-controller@0 {
   compatible = "snps,dw-apb-gpio-port";
   bank-name = "porta";
   gpio-controller;
   #gpio-cells = <2>;
   snps,nr-gpios = <32>;
   reg = <0>;
  };
 };

 gpio1: gpio@03021000 {
  compatible = "snps,dw-apb-gpio";
  reg = <0x0 0x03021000 0x0 0x1000>;
  #address-cells = <1>;
  #size-cells = <0>;

  portb: gpio-controller@1 {
   compatible = "snps,dw-apb-gpio-port";
   bank-name = "portb";
   gpio-controller;
   #gpio-cells = <2>;
   snps,nr-gpios = <32>;
   reg = <0>;
  };
 };

 gpio2: gpio@03022000 {
  compatible = "snps,dw-apb-gpio";
  reg = <0x0 0x03022000 0x0 0x1000>;
  #address-cells = <1>;
  #size-cells = <0>;

  portc: gpio-controller@2 {
   compatible = "snps,dw-apb-gpio-port";
   bank-name = "portc";
   gpio-controller;
   #gpio-cells = <2>;
   snps,nr-gpios = <32>;
   reg = <0>;
  };
 };

 gpio3: gpio@03023000 {
  compatible = "snps,dw-apb-gpio";
  reg = <0x0 0x03023000 0x0 0x1000>;
  #address-cells = <1>;
  #size-cells = <0>;

  portd: gpio-controller@3 {
   compatible = "snps,dw-apb-gpio-port";
   bank-name = "portd";
   gpio-controller;
   #gpio-cells = <2>;
   snps,nr-gpios = <32>;
   reg = <0>;
  };
 };

 gpio4: gpio@05021000 {
  compatible = "snps,dw-apb-gpio";
  reg = <0x0 0x05021000 0x0 0x1000>;
  #address-cells = <1>;
  #size-cells = <0>;

  porte: gpio-controller@4 {
   compatible = "snps,dw-apb-gpio-port";
   bank-name = "porte";
   gpio-controller;
   #gpio-cells = <2>;
   snps,nr-gpios = <32>;
   reg = <0>;
  };
 };

 i2c0: i2c@04000000 {
  compatible = "snps,designware-i2c";
  clocks = <&clk 111>;
  reg = <0x0 0x04000000 0x0 0x1000>;
  clock-frequency = <400000>;

  #size-cells = <0x0>;
  #address-cells = <0x1>;
  resets = <&rst 27>;
  reset-names = "i2c0";
 };

 i2c1: i2c@04010000 {
  compatible = "snps,designware-i2c";
  clocks = <&clk 111>;
  reg = <0x0 0x04010000 0x0 0x1000>;
  clock-frequency = <400000>;

  #size-cells = <0x0>;
  #address-cells = <0x1>;
  resets = <&rst 28>;
  reset-names = "i2c1";
 };

 i2c2: i2c@04020000 {
  compatible = "snps,designware-i2c";
  clocks = <&clk 111>;
  reg = <0x0 0x04020000 0x0 0x1000>;
  clock-frequency = <100000>;

  #size-cells = <0x0>;
  #address-cells = <0x1>;
  resets = <&rst 29>;
  reset-names = "i2c2";
 };

 i2c3: i2c@04030000 {
  compatible = "snps,designware-i2c";
  clocks = <&clk 111>;
  reg = <0x0 0x04030000 0x0 0x1000>;
  clock-frequency = <400000>;

  #size-cells = <0x0>;
  #address-cells = <0x1>;
  resets = <&rst 30>;
  reset-names = "i2c3";
 };

 i2c4: i2c@04040000 {
  compatible = "snps,designware-i2c";
  clocks = <&clk 111>;
  reg = <0x0 0x04040000 0x0 0x1000>;
  clock-frequency = <400000>;

  #size-cells = <0x0>;
  #address-cells = <0x1>;
  resets = <&rst 31>;
  reset-names = "i2c4";
 };

 eth_csrclk: eth_csrclk {
  clock-output-names = "eth_csrclk";
  clock-frequency = <250000000>;
  #clock-cells = <0x0>;
  compatible = "fixed-clock";
 };

 eth_ptpclk: eth_ptpclk {
  clock-output-names = "eth_ptpclk";
  clock-frequency = <50000000>;
  #clock-cells = <0x0>;
  compatible = "fixed-clock";
 };

 stmmac_axi_setup: stmmac-axi-config {
  snps,wr_osr_lmt = <1>;
  snps,rd_osr_lmt = <2>;
  snps,blen = <4 8 16 0 0 0 0>;
 };

 mtl_rx_setup: rx-queues-config {
  snps,rx-queues-to-use = <1>;
  queue0 {};
 };

 mtl_tx_setup: tx-queues-config {
  snps,tx-queues-to-use = <1>;
  queue0 {};
 };

 ethernet0: ethernet@4070000 {
  compatible = "cvitek,ethernet";
  reg = <0x0 0x04070000 0x0 0x10000>;
  clock-names = "stmmaceth", "ptp_ref";
  clocks = <&eth_csrclk>, <&eth_ptpclk>;


  tx-fifo-depth = <8192>;
  rx-fifo-depth = <8192>;

  snps,multicast-filter-bins = <0>;
  snps,perfect-filter-entries = <1>;

  snps,txpbl = <8>;
  snps,rxpbl = <8>;
  snps,aal;

  snps,axi-config = <&stmmac_axi_setup>;
  snps,mtl-rx-config = <&mtl_rx_setup>;
  snps,mtl-tx-config = <&mtl_tx_setup>;

  phy-mode = "rmii";
 };

 sd:cv-sd@4310000 {
  compatible = "cvitek,cv180x-sd";
  reg = <0x0 0x4310000 0x0 0x1000>;
  reg-names = "core_mem";
  bus-width = <4>;
  cap-sd-highspeed;
  cap-mmc-highspeed;
  sd-uhs-sdr12;
  sd-uhs-sdr25;
  sd-uhs-sdr50;
  sd-uhs-sdr104;
  no-sdio;
  no-mmc;

  src-frequency = <375000000>;
  min-frequency = <400000>;
  max-frequency = <200000000>;
  64_addressing;
  reset_tx_rx_phy;
  reset-names = "sdhci";
  pll_index = <0x6>;
  pll_reg = <0x3002070>;
  cvi-cd-gpios = <&porta 13 1>;
 };

 wifisd:wifi-sd@4320000 {
  compatible = "cvitek,cv180x-sdio";
  bus-width = <4>;
  reg = <0x0 0x4320000 0x0 0x1000>;
  reg_names = "core_mem";
  src-frequency = <375000000>;
  min-frequency = <400000>;
  max-frequency = <50000000>;
  64_addressing;
  reset_tx_rx_phy;
  non-removable;
  pll_index = <0x7>;
  pll_reg = <0x300207C>;
  no-mmc;
  no-sd;
  status = "disabled";
 };

 i2s_mclk: i2s_mclk {
  clock-output-names = "i2s_mclk";
  clock-frequency = <24576000>;
  #clock-cells = <0x0>;
  compatible = "fixed-clock";
 };

 i2s_subsys {
  compatible = "cvitek,i2s_tdm_subsys";
  reg = <0x0 0x04108000 0x0 0x100>;
  clocks = <&i2s_mclk>, <&clk 4>,
   <&clk 42>, <&clk 43>,
   <&clk 44>, <&clk 45>;
  clock-names = "i2sclk", "clk_a0pll",
   "clk_sdma_aud0", "clk_sdma_aud1",
   "clk_sdma_aud2", "clk_sdma_aud3";
  master_base = <0x04110000>;
 };

 i2s0: i2s@04100000 {
  compatible = "cvitek,cv1835-i2s";
  reg = <0x0 0x04100000 0x0 0x2000>;
  clocks = <&i2s_mclk 0>;
  clock-names = "i2sclk";
  dev-id = <0>;
  #sound-dai-cells = <0>;
  dmas = <&dmac 0 1 1>;
  dma-names = "rx";
  capability = "rx";
  mclk_out = "false";
 };

 i2s1: i2s@04110000 {
  compatible = "cvitek,cv1835-i2s";
  reg = <0x0 0x04110000 0x0 0x2000>;
  clocks = <&i2s_mclk 0>;
  clock-names = "i2sclk";
  dev-id = <1>;
  #sound-dai-cells = <0>;
  dmas = <&dmac 2 1 1
   &dmac 3 1 1>;
  dma-names = "rx", "tx";
  capability = "txrx";
  mclk_out = "false";
 };

 i2s2: i2s@04120000 {
  compatible = "cvitek,cv1835-i2s";
  reg = <0x0 0x04120000 0x0 0x2000>;
  clocks = <&i2s_mclk 0>;
  clock-names = "i2sclk";
  dev-id = <2>;
  #sound-dai-cells = <0>;
  dmas = <&dmac 6 1 1
   &dmac 1 1 1>;
  dma-names = "rx", "tx";
  capability = "txrx";
  mclk_out = "false";

 };

 i2s3: i2s@04130000 {
  compatible = "cvitek,cv1835-i2s";
  reg = <0x0 0x04130000 0x0 0x2000>;
  clocks = <&i2s_mclk 0>;
  clock-names = "i2sclk";
  dev-id = <3>;
  #sound-dai-cells = <0>;
  dmas = <&dmac 7 1 1>;
  dma-names = "tx";
  capability = "tx";
  mclk_out = "true";
 };

 adc: adc@0300A100 {
  compatible = "cvitek,cv182xaadc";
  reg = <0x0 0x0300A100 0x0 0x100>;
  clocks = <&i2s_mclk 0>;
  clock-names = "i2sclk";
  clk_source = <0x04130000>;
 };

 dac: dac@0300A000 {
  compatible = "cvitek,cv182xadac";
  reg = <0x0 0x0300A000 0x0 0x100>;
  clocks = <&i2s_mclk 0>;
  clock-names = "i2sclk";
 };

 pdm: pdm@0x041D0C00 {
  compatible = "cvitek,cv1835pdm";
  reg = <0x0 0x041D0C00 0x0 0x100>;
  clocks = <&i2s_mclk 0>;
  clock-names = "i2sclk";
 };

 sound_adc {
  compatible = "cvitek,cv182xa-adc";
  cvi,model = "CV182XA";
  cvi,card_name = "cv182xa_adc";
 };

 sound_dac {
  compatible = "cvitek,cv182xa-dac";
  cvi,model = "CV182XA";
  cvi,card_name = "cv182xa_dac";
 };

 sound_PDM {
  compatible = "cvitek,cv182x-pdm";
  cvi,model = "CV182X";
  cvi,card_name = "cv182x_internal_PDM";
 };

 wifi_pin {
  compatible = "cvitek,wifi-pin";
  poweron-gpio = <&porta 18 0>;
  wakeup-gpio = <&porte 7 0>;
 };

 bt_pin {
  compatible = "cvitek,bt-pin";
  poweron-gpio = <&porte 9 0>;
 };

 mipi_rx: cif {
  compatible = "cvitek,cif";
  reg = <0x0 0x0a0c2000 0x0 0x2000>, <0x0 0x0a0d0000 0x0 0x1000>,
        <0x0 0x0a0c4000 0x0 0x2000>, <0x0 0x03001c30 0x0 0x30>;
  reg-names = "csi_mac0", "csi_wrap0", "csi_mac1", "pad_ctrl";
  snsr-reset = <&porta 2 1>, <&porta 2 1>, <&porta 2 1>;
  resets = <&rst 70>, <&rst 72>,
   <&rst 71>, <&rst 73>;
  reset-names = "phy0", "phy1", "phy-apb0", "phy-apb1";
  clocks = <&clk 88>, <&clk 89>, <&clk 133>,
    <&clk 3>, <&clk 5>, <&clk 2>;
  clock-names = "clk_cam0", "clk_cam1", "clk_sys_2",
         "clk_mipimpll", "clk_disppll", "clk_fpll";
 };

 sys {
  compatible = "cvitek,sys";
 };

 base {
  compatible = "cvitek,base";
  reg = <0x0 0x0a0c8000 0x0 0x20>;
  reg-names = "vip_sys";
 };

 vi {
  compatible = "cvitek,vi";
  reg = <0x0 0x0a000000 0x0 0x80000>;
  clocks = <&clk 77>, <&clk 78>,
    <&clk 133>, <&clk 151>,
    <&clk 76>, <&clk 144>,
    <&clk 154>, <&clk 92>,
    <&clk 90>, <&clk 91>,
    <&clk 156>;
  clock-names = "clk_sys_0", "clk_sys_1", "clk_sys_2", "clk_sys_3",
     "clk_axi", "clk_csi_be", "clk_raw", "clk_isp_top",
     "clk_csi_mac0", "clk_csi_mac1", "clk_csi_mac2";
  clock-freq-vip-sys1 = <300000000>;
 };

 vpss {
  compatible = "cvitek,vpss";
  reg = <0x0 0x0a080000 0x0 0x10000>, <0x0 0x0a0d1000 0x0 0x100>;
  reg-names = "sc";
  clocks = <&clk 77>, <&clk 78>,
   <&clk 133>, <&clk 93>,
   <&clk 94>, <&clk 95>,
   <&clk 96>, <&clk 97>,
   <&clk 98>, <&clk 99>;
  clock-names = "clk_sys_0", "clk_sys_1",
   "clk_sys_2", "clk_img_d",
   "clk_img_v", "clk_sc_top",
   "clk_sc_d", "clk_sc_v1",
   "clk_sc_v2", "clk_sc_v3";
  clock-freq-vip-sys1 = <300000000>;
 };

 dwa {
  compatible = "cvitek,dwa";
  reg = <0x0 0x0a0c0000 0x0 0x1000>;
  reg-names = "dwa";
  clocks = <&clk 77>, <&clk 78>,
   <&clk 133>, <&clk 151>,
   <&clk 152>, <&clk 100>;
  clock-names = "clk_sys_0", "clk_sys_1",
   "clk_sys_2", "clk_sys_3",
   "clk_sys_4", "clk_dwa";
  clock-freq-vip-sys1 = <300000000>;
 };

 rgn {
  compatible = "cvitek,rgn";
 };

 vcodec {
  compatible = "cvitek,asic-vcodec";
  reg = <0x0 0x0B020000 0x0 0x10000>,<0x0 0x0B010000 0x0 0x10000>,<0x0 0x0B030000 0x0 0x100>,
        <0x0 0x0B058000 0x0 0x100>,<0x0 0x0B050000 0x0 0x400>;
  reg-names = "h265","h264","vc_ctrl","vc_sbm","vc_addr_remap";
  clocks = <&clk 80>,
   <&clk 82>, <&clk 86>,
   <&clk 83>, <&clk 87>,
   <&clk 81>, <&clk 132>,
   <&clk 139>, <&clk 136>;
  clock-names = "clk_axi_video_codec",
   "clk_h264c", "clk_apb_h264c",
   "clk_h265c", "clk_apb_h265c",
   "clk_vc_src0", "clk_vc_src1",
   "clk_vc_src2", "clk_cfg_reg_vc";
 };

 jpu {
  compatible = "cvitek,asic-jpeg";
  reg = <0x0 0x0B000000 0x0 0x300>,<0x0 0x0B030000 0x0 0x100>,<0x0 0x0B058000 0x0 0x100>;
  reg-names = "jpeg","vc_ctrl","vc_sbm";
  clocks = <&clk 80>,
   <&clk 84>, <&clk 85>,
   <&clk 81>, <&clk 132>,
   <&clk 139>, <&clk 136>;
  clock-names = "clk_axi_video_codec",
   "clk_jpeg", "clk_apb_jpeg",
   "clk_vc_src0", "clk_vc_src1",
   "clk_vc_src2", "clk_cfg_reg_vc";
  resets = <&rst 4>;
  reset-names = "jpeg";
 };

 cvi_vc_drv {
  compatible = "cvitek,cvi_vc_drv";
  reg = <0x0 0x0B030000 0x0 0x100>,<0x0 0x0B058000 0x0 0x100>,<0x0 0x0B050000 0x0 0x400>;
  reg-names = "vc_ctrl","vc_sbm","vc_addr_remap";
 };

 rtos_cmdqu {
  compatible = "cvitek,rtos_cmdqu";
  reg = <0x0 0x01900000 0x0 0x1000>;
  reg-names = "mailbox";
 };

 usb: usb@04340000 {
  compatible = "cvitek,cv182x-usb";
  reg = <0x0 0x04340000 0x0 0x10000>,
   <0x0 0x03006000 0x0 0x58>;
  dr_mode = "otg";
  g-use-dma;
  g-rx-fifo-size = <536>;
  g-np-tx-fifo-size = <32>;
  g-tx-fifo-size = <768 512 512 384 128 128>;
  clocks = <&clk 68>,
    <&clk 69>,
    <&clk 70>,
    <&clk 71>,
    <&clk 72>;
  clock-names = "clk_axi", "clk_apb", "clk_125m", "clk_33k", "clk_12m";
  vbus-gpio = <&portb 6 0>;
  status = "okay";
 };

 thermal:thermal@030E0000 {
  compatible = "cvitek,cv180x-thermal";
  reg = <0x0 0x030E0000 0x0 0x10000>;
  clocks = <&clk 17>;
  clock-names = "clk_tempsen";
  reset-names = "tempsen";
  #thermal-sensor-cells = <1>;
 };
# 817 "official_device/cv180x_base.dtsi"
 thermal-zones {
  soc_thermal_0: soc_thermal_0 {
   polling-delay-passive = <1000>;
   polling-delay = <1000>;
   thermal-sensors = <&thermal 0>;

   trips {
    soc_thermal_trip_0: soc_thermal_trip_0 {
     temperature = <100000>;
     hysteresis = <5000>;
     type = "passive";
    };

    soc_thermal_trip_1: soc_thermal_trip_1 {
     temperature = <110000>;
     hysteresis = <5000>;
     type = "passive";
    };

    soc_thermal_crtical_0: soc_thermal_crtical_0 {
     temperature = <130000>;
     hysteresis = <0>;
     type = "critical";
    };
   };
  };
 };
# 852 "official_device/cv180x_base.dtsi"
 cviaudio_core {
  compatible = "cvitek,audio";
 };

 audio_clock: audio_clock {
  compatible = "fixed-clock";
  #clock-cells = <0>;



  clock-frequency = <24576000>;

  };


 aliases {
  i2c0 = &i2c0;
  i2c1 = &i2c1;
  i2c2 = &i2c2;
  i2c3 = &i2c3;
  i2c4 = &i2c4;
  serial0 = &uart0;
  serial1 = &uart1;
  serial2 = &uart2;
  serial3 = &uart3;
  serial4 = &uart4;
  ethernet0 = &ethernet0;
 };

 chosen {
  stdout-path = "serial0";
 };
};
# 23 "official_device/cv180x_base_riscv.dtsi" 2

/ {
 model = "Cvitek. CV180X ASIC. C906.";

 #size-cells = <0x2>;
 #address-cells = <0x2>;

 c906_cpus:cpus {
  #address-cells = <0x01>;
  #size-cells = <0x00>;
  timebase-frequency = <25000000>;

  cpu-map {

   cluster0 {

    core0 {
     cpu = <0x01>;
    };
   };
  };

  cpu@0 {
   device_type = "cpu";
   reg = <0x00>;
   status = "okay";
   compatible = "riscv";
   riscv,isa = "rv64imafdvcsu";
   mmu-type = "riscv,sv39";
   clock-frequency = <25000000>;

   cpu0_intc: interrupt-controller {
    #interrupt-cells = <0x01>;
    interrupt-controller;
    compatible = "riscv,cpu-intc";
   };
  };
 };

 soc {
  #address-cells = <0x02>;
  #size-cells = <0x02>;
  compatible = "simple-bus";
  ranges;

  plic0: interrupt-controller@70000000 {
   riscv,ndev = <101>;
   riscv,max-priority = <0x07>;
   reg-names = "control";
   reg = <0x00 0x70000000 0x00 0x4000000>;
   interrupts-extended = <&cpu0_intc 0xffffffff &cpu0_intc 0x09>;
   interrupt-controller;
   compatible = "riscv,plic0";
   #interrupt-cells = <0x02>;
   #address-cells = <0x00>;
  };

  clint@74000000 {
   interrupts-extended = <&cpu0_intc 0x03 &cpu0_intc 0x07>;
   reg = <0x00 0x74000000 0x00 0x10000>;
   compatible = "riscv,clint0";
   clint,has-no-64bit-mmio;
  };

 };


 cv180x_cooling:cv180x_cooling {
  clocks = <&clk 149>, <&clk 12>;
  clock-names = "clk_cpu", "clk_tpu_axi";
  dev-freqs = <850000000 500000000>,
   <425000000 375000000>,
   <425000000 300000000>;
  compatible = "cvitek,cv180x-cooling";
  #cooling-cells = <2>;
 };

 tpu {
  interrupts = <75 4>,
    <76 4>;
  interrupt-names = "tiu_irq", "tdma_irq";
  interrupt-parent = <&plic0>;
 };

 mon {
  interrupts = <93 4>;
  interrupt-names = "mon_irq";
  interrupt-parent = <&plic0>;
 };

 wiegand0 {
  interrupts = <64 4>;
  interrupt-parent = <&plic0>;
 };

 wiegand1 {
  interrupts = <65 4>;
  interrupt-parent = <&plic0>;
 };

 wiegand2 {
  interrupts = <66 4>;
  interrupt-parent = <&plic0>;
 };

 saradc {
  interrupts = <100 1>;
  interrupt-parent = <&plic0>;
 };

 rtc {
  interrupts = <17 4>;
  interrupt-parent = <&plic0>;
 };

 sysdma_remap {
  int_mux = <0x7FC00>;
 };

 dmac: dma@0x4330000 {
  interrupts = <29 4>;
  interrupt-parent = <&plic0>;
 };

 watchdog0: cv-wd@0x3010000 {
  interrupts = <58 4>;
 };

 spinand:cv-spinf@4060000 {
  interrupts = <39 4>;
  interrupt-parent = <&plic0>;
 };

 spif:cvi-spif@10000000 {
  interrupts = <95 4>;
  interrupt-parent = <&plic0>;
 };

 spi0:spi0@04180000 {
  interrupts = <54 4>;
  interrupt-parent = <&plic0>;
 };

 spi1:spi1@04190000 {
  interrupts = <55 4>;
  interrupt-parent = <&plic0>;
 };

 spi2:spi2@041A0000 {
  interrupts = <56 4>;
  interrupt-parent = <&plic0>;
 };

 spi3:spi3@041B0000 {
  interrupts = <57 4>;
  interrupt-parent = <&plic0>;
 };

 uart0: serial@04140000 {
  interrupts = <44 4>;
  interrupt-parent = <&plic0>;
 };

 uart1: serial@04150000 {
  interrupts = <45 4>;
  interrupt-parent = <&plic0>;
 };

 uart2: serial@04160000 {
  interrupts = <46 4>;
  interrupt-parent = <&plic0>;
 };

 uart3: serial@04170000 {
  interrupts = <47 4>;
  interrupt-parent = <&plic0>;
 };

 uart4: serial@041C0000 {
  interrupts = <48 4>;
  interrupt-parent = <&plic0>;
 };

 gpio0: gpio@03020000 {
  porta: gpio-controller@0 {
   interrupt-controller;
   interrupts = <60 4>;
   interrupt-parent = <&plic0>;
  };
 };

 gpio1: gpio@03021000 {
  portb: gpio-controller@1 {
   interrupt-controller;
   interrupts = <61 4>;
   interrupt-parent = <&plic0>;
  };
 };

 gpio2: gpio@03022000 {
  portc: gpio-controller@2 {
   interrupt-controller;
   interrupts = <62 4>;
   interrupt-parent = <&plic0>;
  };
 };

 gpio3: gpio@03023000 {
  portd: gpio-controller@3 {
   interrupt-controller;
   interrupts = <63 4>;
   interrupt-parent = <&plic0>;
  };
 };

 gpio4: gpio@05021000 {
  porte: gpio-controller@4 {
   interrupt-controller;
   interrupts = <70 4>;
   interrupt-parent = <&plic0>;
  };
 };

 i2c0: i2c@04000000 {
  interrupts = <49 4>;
  interrupt-parent = <&plic0>;
 };

 i2c1: i2c@04010000 {
  interrupts = <50 4>;
  interrupt-parent = <&plic0>;
 };

 i2c2: i2c@04020000 {
  interrupts = <51 4>;
  interrupt-parent = <&plic0>;
 };

 i2c3: i2c@04030000 {
  interrupts = <52 4>;
  interrupt-parent = <&plic0>;
 };

 i2c4: i2c@04040000 {
  interrupts = <53 4>;
  interrupt-parent = <&plic0>;
 };

 ethernet0: ethernet@4070000 {
  interrupt-names = "macirq";
  interrupts = <31 4>;
  interrupt-parent = <&plic0>;
 };






 sd:cv-sd@4310000 {
  interrupts = <36 4>;
  interrupt-parent = <&plic0>;
 };

 i2s0: i2s@04100000 {
  interrupts = <40 4>;
  interrupt-parent = <&plic0>;
 };

 i2s1: i2s@04110000 {
  interrupts = <41 4>;
  interrupt-parent = <&plic0>;
 };

 i2s2: i2s@04120000 {
  interrupts = <42 4>;
  interrupt-parent = <&plic0>;
 };

 i2s3: i2s@04130000 {
  interrupts = <43 4>;
  interrupt-parent = <&plic0>;
 };

 vi {
  interrupts = <24 4>;
  interrupt-parent = <&plic0>;
  interrupt-names = "isp";
 };

 vcodec {
  interrupts = <22 4>,
        <21 4>,
        <23 4>;
  interrupt-names = "h265","h264","sbm";
  interrupt-parent = <&plic0>;
 };

 jpu {
  interrupts = <20 4>;
  interrupt-names = "jpeg";
  interrupt-parent = <&plic0>;
 };

 rtos_cmdqu {
  interrupts = <101 4>;
  interrupt-names = "mailbox";
  interrupt-parent = <&plic0>;
 };

 wifisd:wifi-sd@4320000 {
  interrupts = <38 4>;
  interrupt-parent = <&plic0>;
 };

 mipi_rx: cif {
  interrupts = <26 4>,
        <27 4>;
  interrupt-names = "csi0", "csi1";
  interrupt-parent = <&plic0>;
 };







 vpss {
  interrupts = <25 4>;
  interrupt-names = "sc";
  interrupt-parent = <&plic0>;
 };

 dwa {
  interrupts = <28 4>;
  interrupt-names = "dwa";
  interrupt-parent = <&plic0>;
 };

 usb: usb@04340000 {
  interrupts = <30 4>;
  interrupt-parent = <&plic0>;
 };

 thermal:thermal@030E0000 {
  interrupts = <16 4>;
  interrupt-names = "tempsen";
  interrupt-parent = <&plic0>;
 };

};
# 3 "official_device/cv1800b_milkv_duo_sd.dts" 2
# 1 "official_device/cv180x_asic_qfn.dtsi" 1
&sd {
 no-1-8-v;
};

&mipi_rx{
 snsr-reset = <&portc 13 1>, <&portc 13 1>, <&portc 13 1>;
};

&dac{
 mute-gpio-r = <&porte 2 1>;
};

&spi0 {
 status = "disabled";
 num-cs = <1>;
 spidev@0 {
  compatible = "rohm,dh2228fv";
  spi-max-frequency = <1000000>;
  reg = <0>;
 };
};

&spi1 {
 status = "disabled";
 num-cs = <1>;
 spidev@0 {
  compatible = "rohm,dh2228fv";
  spi-max-frequency = <1000000>;
  reg = <0>;
 };
};

&spi2 {
 status = "disabled";
 num-cs = <1>;
 spidev@0 {
 compatible = "rohm,dh2228fv";
  spi-max-frequency = <1000000>;
  reg = <0>;
 };
};

&spi3 {
 status = "okay";
 num-cs = <1>;
 spidev@0 {
  compatible = "rohm,dh2228fv";
  spi-max-frequency = <1000000>;
  reg = <0>;
 };
};

/ {
 /delete-node/ wifi-sd@4320000;
 /delete-node/ i2s@04110000;
 /delete-node/ i2s@04120000;
 /delete-node/ sound_ext1;
 /delete-node/ sound_ext2;
 /delete-node/ sound_PDM;

 wifi_pin {
  compatible = "cvitek,wifi-pin";
  poweron-gpio = <&porte 2 0>;
  wakeup-gpio = <&porte 6 0>;
 };

};
# 4 "official_device/cv1800b_milkv_duo_sd.dts" 2
# 1 "official_device/cv180x_asic_sd.dtsi" 1
/ {
 /delete-node/ cv-emmc@4300000;
 /delete-node/ cv-spinf@4060000;
};
# 5 "official_device/cv1800b_milkv_duo_sd.dts" 2
# 1 "official_device/cv180x_default_memmap.dtsi" 1
/ {
 memory@80000000 {
  device_type = "memory";
  reg = <0x00 0x80000000 0x00 0x3f40000>;
 };


 fast_image {
  compatible = "cvitek,rtos_image";
  reg-names = "rtos_region";
  reg = <0x0 0x83f40000 0x0 0xc0000>;
  ion-size = <0x0>;
 };

 reserved-memory {
  #size-cells = <0x2>;
  #address-cells = <0x2>;
  ranges;

  ion_reserved: ion {
   compatible = "ion-region";
   alloc-ranges = <0x0 0x83f40000 0 0x0>;
   size = <0x0 0x0>;
  };
 };
};
# 6 "official_device/cv1800b_milkv_duo_sd.dts" 2



&mipi_rx{
 snsr-reset = <&portc 8 1>, <&portc 8 1>, <&portc 8 1>;
};

&spi2 {
 status = "okay";

 spidev@0 {
  status = "okay";
 };
};

&uart4 {
 status = "okay";
};

&i2c1 {
       status = "okay";
       clock-frequency = <100000>;
};

/ {

};