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Mike Zhou/基于FPGA-Verilog HDL的TCD1206SUP图像传感器驱动电路设计

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TCD1206.qsf 1.53 KB
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网易独家音乐人Mike Zhou 提交于 2024-10-16 02:33 . 1
set_global_assignment -name TOP_LEVEL_ENTITY TCD1206
set_global_assignment -name LAST_QUARTUS_VERSION 9.0
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE EP2C5Q208C8
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name MISC_FILE "C:/Project/Quartus Project/光电1801周久韧.20181109010.图像传感器驱动课程设计/TCD1206/TCD1206.dpf"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_10 -to CLK
set_location_assignment PIN_11 -to RST
set_location_assignment PIN_3 -to CR1
set_location_assignment PIN_4 -to CR2
set_location_assignment PIN_5 -to RS
set_location_assignment PIN_6 -to SH
set_global_assignment -name ZIP_VECTOR_WAVEFORM_FILE db/TCD1206.sim.cvwf
set_global_assignment -name VECTOR_WAVEFORM_FILE TCD1206.vwf
set_global_assignment -name VERILOG_FILE TCD1206.v
set_global_assignment -name BDF_FILE TCD1206_bdf.bdf
set_global_assignment -name MISC_FILE "E:/Quartus Project/光电1801周久韧.20181109010.图像传感器驱动课程设计/TCD1206/TCD1206.dpf"
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https://gitee.com/Mike_Zhou_Group/TCD1206SUP_FPGA.git
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TCD1206SUP_FPGA
基于FPGA-Verilog HDL的TCD1206SUP图像传感器驱动电路设计
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